Field of the Technology
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
A 3D memory device can include an array of NAND strings of memory cells. The memory device can include an integrated circuit substrate, and a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips configured as ground select lines (GSL), a plurality of intermediate planes of conductive strips configured as word lines (WLs), and a top plane of conductive strips configured as string select lines (SSLs). Active strips are disposed on the plurality of stacks, and arranged orthogonally over the plurality of stacks. Memory cells including charge storage structures are formed at cross-points between side surfaces of the active strips on the plurality of stacks and the word lines.
A 3D memory device can include different metal layers for routing word lines, string select lines, ground select lines, bit lines connected to the active strips, etc. For example, a first metal layer over the stacks of conductive strips can include conductor lines for routing local source lines, a second metal layer over the first metal layer can include conductor lines for routing bit lines, and a third metal layer over the second metal layer can include conductor lines for routing word lines, string select lines and ground select lines. String select lines (SSLs) in the top plane of conductive strips are routed to a row decoder in the 3D memory device. The row decoder decodes SSL and GSL lines for read, write and erase operations on memory cells in the 3D memory device. The third metal layer includes respective conductor lines for respective string select lines in the 3D memory device. For instance, for 32 strings select lines in 32 NAND strings, the third metal layer includes 32 conductor lines routed to the 32 string select lines. Routing efficiency regarding string select lines, at a metal level such as the third metal level, is affected by string select structures.
It is desirable to provide efficient string select structures for three-dimensional integrated circuit memory.